2. AES Algorithm.
3. Viterbi Algorithm-Decoder.
4. Viterbi Algorithm-Encoder.
5. DDRR Algorithm.
6. Deficit Round Robin Algorithm.
7. FPGA based Generation of High Frequency Carrier for Pulse Compression using CORDIC Algorithm.
8. Dynamic Round Robin Algorithm.
9. Watermarking in a Secure Still Digital Camera Design.
10. Implementation of Lossless Data Compression and Decompression using (Parallel Dictionary Lempel Ziv Welch) PDLZW Algorithm.
11. 8/16/32 Point Fast Fourier Transform Algorithm.
12. Booths Algorithm.
13. VLSI Implementation of High Speed Reed‐Solomon Decoder.
14. UART.
15. On the Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFICs.
16. VLSI implementation of Cascaded-Integrator-Comb Filter.
17. VLSI implementation of Wave-Digital-Filters.
18. VLSI implementation of Notch filters.
19. VLSI implementation of FIR filters.
20. Method for VLSI implementation of fractional sample rate converter (FSRC) and corresponding converter architecture.
21. Area optimized architecture and VLSI implementation of RC5 ALGORITHM.
22. VLSI implementation of canonical Huffman decoder.
23. Area optimized architecture and VLSI implementation of RC5 Decryption ALGORITHM.
24. VLSI implementation of canonical Huffman encoder.
25. VLSI implementation of canonical Huffman algorithm.
26. VLSI implementation of Stegnography.
27. Area optimized architecture and VLSI implementation of RC5 Encryption ALGORITHM.
28. 16 Bit fixed point DSP Processor.
29. VLSI Implementation of Address Generation Coprocessor.
30. Implementation of AHDB (Adaptive Huffman Dynamic Block) Algorithm.
31. Implementation of LZW Data Compression Algorithm.
32. A Low Power Multiplier with SPST.
33. A Low Power VLSI Implementation for JPEG2000 Codec.
34. A Verilog Implementation of Built In Self Test of UART.
35. Fuzzy based PID Controller using VHDL for Transportation Application.
36. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication.
37. Power conscious test synthesis and scheduling.
38. The CSI Multimedia Architecture.
39. An Area-Efficient Universal Cryptography Processor for Smart Cards.
40. Block-Based Multi period Dynamic Memory Design for Low Data-Retention Power.
41. Cost effective SHA hardware accelerators.
42. Scalable multi giga bit pattern matching for packet inspection.
43. An FPGA-based Architecture for Real Time Image Feature Extraction.
44. Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications.
45. An Efficient Spurious Power Suppression Technique (SPST) and its Applications on MPEG-4 AVClH.264 Transform Coding Design.
46. Synchronization in Software Radios - Carrier and Timing Recovery Using FPGAs.
47. Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor.
48. High-Speed Booth Encoded Parallel Multiplier Design.
49. Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications.
50. Implementation of IEEE 802.11a WLAN Baseband Processor.
51. An Efficient Spurious Power Suppression Technique (SPST) and its Applications on MPEG-4 AVClH.264 Transform Coding Design.
VLSI WITH MATLAB
1. DCT Modified Algorithms Implemented in FPGA Chips for Real-Time Image Compression.
2. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication.
3. DCT and IDCT Implementations on Different FPGA Technologies.
4. Implementation of Watermarking Algorithm.
5. Secure transmitting and receiving text data in communication systems.
6. VLSI architecture for Cryptography algorithm.
7. Image filtering using VLSI.
8. Implementation of Edge detection method.
9. Robust Image Watermarking Based on Multiband Wavelets and Empirical Mode Decomposition.
10. A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design.